As shown in FIG. 1, a typical computer system (10) has, among other components, a microprocessor (12), one or more forms of memory (14), integrated circuits (16) having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another to accomplish the tasks of the computer system (10).
In order to properly accomplish such tasks, the computer system (10) relies on the basis of time to coordinate its various operations. To this end, one or more clock signals are provided to various components within the computer system (10). The providing of these clock signals is achieved through the use of clock distribution networks. A clock distribution network distributes a clock signal to various components that depend in order to perform operations in a timely, accurate, and predictable manner.
FIG. 2 shows a typical clock distribution network (20) for an integrated circuit. The clock distribution network (20) provides, via one or more clock buffers/drivers (22) clock signals to a global clock grid (24) and one or more local clock grids (26), latches (28), and/or flip-flops (30). Because the performance of a computer system so heavily relies on the accurate and timely distribution of clock signals to the various components of the integrated circuit, timing verification of clock distribution networks (also referred to as “clock network verification”) is an important step in the design cycle of an integrated circuit.
Such timing verification typically involves reducing the integrated circuit to a manageable size and then simulating operations on the reduced circuit. The integrated circuit is often reduced at a transistor level to achieve better performance and shorter design cycle time for the clock distribution network timing verification process.
As computers continue to operate at ever-increasing clock speeds, circuit complexity, and sizes, the timing verification for clock distribution networks is becoming an issue of critical importance in integrated circuit design. Accordingly, the run time needed to produce precise clock system timing evaluations during a design and development stage has increased significantly, and often violates industry chip design schedules.
Referring to transistor level reduction, transistors and transistor-based circuits, which are often used to amplify clock signals that propagate through a clock distribution network, are typically built to fit design requirements and constraints such as chip area availability, power availability, timing budgets, etc. However, such circuit configurations are difficult to handle directly by accurate timing verification simulation tools due to the large complexity and size of modem integrated circuits. Reduction and subsequent simulation of such circuit configurations can cause long simulation times that result in design cycle violations.
FIG. 3 shows a flow process of a typical reduction for clock network verification. Before actual reduction, a circuit layout or design is stored in some accessible database (40). A transistor extraction tool is applied to the circuit layout stored in the database (step 42), where after the transistor extraction tool generates a transistor circuit netlist (44). Similarly, a parasitics extraction tool is applied to the circuit layout stored in the database (step 46), where after the parasitics extraction tool generates a parasitics netlist (48).
The transistor circuit netlist and parasitics netlist are then available to a netlist processor stage (step 50), which, it turn, prepares an electrical netlist for simulation (52). A timing simulation tool then simulates the electrical netlist (52) (step 54) and generates timings (56) for the circuit.
FIG. 4 shows an expanded flow process of the netlist processor step shown in FIG. 3. Upon generation of the transistor circuit netlist (44), cell wrapper files for the transistor circuit netlist are generated (step 58). Using the transistors listed in the transistor circuit netlist (44), the cell wrappers generation stage (step 58) encloses each transistor's lower level components in a cell wrapper, or “package.”
Thereafter, the transistor circuit netlist and parasitics netlist go through a voltage source connection stage (step 60) and a library attachments stage (step 62). In the voltage source connection stage (step 60), the wrapped cells are connected to voltage sources specified in the original circuit. The parasitic netlist (48) is also used in the voltage source connection stage (step 60) when connecting the cells to voltage sources to account for the parasitics in the circuit components and connections. In the library attachments stage (step 62), property libraries of the various components within the circuit netlist are attached for use by the timing simulation tool. The wrapper generation stage (step 58), the voltage source connection stage (step 60), and the library attachments stage (step 62) are used to build the overall circuit netlist for more efficient timing simulation. However, as discussed above, with the increasing speeds, complexity, and size of modern integrated circuits, timing simulations as discussed with references to FIGS. 3 and 4 are proving to prone to inaccuracy and are highly time intensive.
One way to reduce the amount of time needed to produce timing evaluations is to use a software tool designed to use less simulation time. However, the accuracy of the timing results that can be produced by such a software tool is usually not great enough to meet timing requirements imposed by clock signal propagation time and skew verification.